The present invention provides techniques for editing circuit design code so that it is compatible with a new programmable integrated circuit (IC), and more particularly, to techniques for converting code describing a circuit design written for a first programmable integrated circuit into code that is compatible with a second programmable integrated circuit.
A programmable logic integrated circuit (IC) is a general purpose IC that can be configured to implement a variety of circuit designs. Programmable logic ICs typically include repeating arrays of programmable logic blocks and memory blocks. Examples of programmable logic ICs include field programmable gate arrays (FPGA), programmable logic devices (PLDs), programmable logic arrays (PLAs), configurable logic arrays, etc.
Hardware circuit designs are typically expressed in computer aided design software using a hardware description language (HDL) language such as Verilog or VHDL. HDL programs of circuit designs that are intended to be programmed into a programmable IC are usually targeted to specific IC architecture.
For example, some FPGA manufacturers provide primitives in their HDL libraries. A primitive is a basic building block that can be used to describe a portion of a circuit design. A multiplier block is an example of a primitive. Primitives are typically provided in HDL libraries to simplify the task of designing a complicated circuit that is targeted for a particular FPGA. Many HDL libraries also have a larger or more complex building block of a hardware circuit (such as a phase locked loop).
Often, users of FPGAs desire to switch from one type of FPGA to another. A user may desire to purchase an FPGA made by a new manufacturer after an FPGA-specific HDL program has already been created describing the user's circuit design. The new manufacturer can increase the chances of obtaining a client's business if the HDL program for the circuit design can be converted to be compatible with the new manufacturer's FPGA. However, it takes a substantial amount of time and effort to manually edit a HDL program so that is compatible with a new FPGA.
Previously known methods have been put forth for converting a circuit design file into a file that is compatible with a different FPGA. These methods require a considerable amount of input from the user at runtime to perform the conversion. During the conversion process, the user has to answer numerous design specific questions.
For example, the user has to identify elements in the circuit design as block boxes. The user also has to describe the implementation of the identified black boxes. To answer these questions, the user must possess a very detailed understanding of the circuit design. To obtain such a level of understanding, the user must spend a considerable amount of time sifting through the circuit design files and the timing constraint files associated with it.
Thus, the design conversion techniques are slow and time consuming. For example, it may take between 5 to 14 days to convert a circuit design, depending on the size and complexity of the design. Design conversions also require a good understanding of the software tools and the architecture primitives for the two FPGAs.
Therefore, it would be desirable to provide more efficient techniques for converting a file containing code that describes a circuit design for a programmable IC into a file that is compatible with a new programmable IC, without requiring the user to have a detailed understanding of the circuit design.